Successive approximation ADC is the name commonly given to an analog-to-digital conversion process in which digital approximations of the input analog voltage are determined on the basis of a binary search. A digital value stored in an n-bit successive approximation register (SAR) is input to a digital-to-analog converter, and a decision is made as to whether the value in the SAR represents an analog voltage that is higher or lower than the input analog value.
The initial value of the SAR is conventionally set to one-half the number that can be represented in the n bits of the SAR. To be more precise, an n-bit register can contain a value of 2n−1, but for purposes of successive approximation, the initial value has the most significant bit set and the others cleared, which translates into a value of 2n/2. If this comparison reveals that the digital approximation is indeed lower than the input voltage, the bit that was initially set remains set, the bit of next greater significance is also set, and another trial commences. If on the other hand, the SAR value is greater than the input analog voltage, the bit that was set for that trial is cleared, the bit of next greater significance is set, and another trial commences. It can be appreciated from this example why a successive approximation approach bears such a similarity to a binary search procedure.
Each bit of the SAR is set or cleared based upon a trial, so the conversion process requires only “n” trials to reach completion. SAR-type algorithms achieve conversion in much less time than a ramp-up technique. A ramp-up type of conversion, for example, requires that the input register of the D/A converter “count-up” by increments of 1 until the analog value is reached. Since each increment of the input register requires a trial to determine whether the analog input level has been reached, many trials may have to be performed before a successful conversion is achieved. There are other types of conversion systems that are even faster than SAR ADC, such as pipeline, flash, and half-flash, but these techniques require much more power than the SAR approach, and are thus unsuitable in many applications.
The main difficulty in A/D conversion generally is settling time. The digital value that is written to the input register (the SAR register in a successive approximation system) produces an analog output at the D/A converter which must be allowed to settle completely before a comparison is performed in order to guarantee system accuracy.
As noted, a conventional SAR converter consists of only a DAC (digital-to-analog converter), a SAR register, control logic, and a single comparator. To generate an N-bit conversion result, each component of the converter is used (or updated) N times in a series of what are known as bit trials. Since only one comparator is used, the converter linearity is only limited by the accuracy of the DAC. The conversion time is dominated by the settling time of the DAC and any comparator preamp, which have to settle to system accuracy every bit trial. Since it is now possible to make very accurate DACs, SAR converters can be made to be extremely accurate. They also require very few analog components. However due to the serial way by which the result is derived, they are inherently slow.
Accordingly, a need arises for an ADC that occupies a relatively small amount of valuable integrated circuit real estate, has a high accuracy, and reaches a conversion result rapidly.